Manufacturers of mobile devices, such as cellular phones, may obtain components of the mobile devices from various sources, including different manufacturers. For example, an application processor in a cellular phone may be obtained from one manufacturer, while an imaging device or camera may be obtained from another manufacturer, and a display may be obtained from yet another manufacturer. The application processor, the imaging device, the display controller, or other types of device may be interconnected using a standards-based or proprietary physical interface. In one example, an imaging device may be connected using the Camera Serial Interface (CSI) defined by the Mobile Industry Processor Interface (MIPI) Alliance. In another example, a display may include an interface that conforms to the Display Serial Interface (DSI) standard specified by MIPI. Further, a multiphase, multi-wire physical layer standard MIPI C-PHY may be utilized to provide high throughput performance over bandwidth-limited channels for connecting displays and cameras to the application processor.
In particular, the multiphase, multi-wire (C-PHY) interface defined by the MIPI Alliance uses three wires or conductors to transmit information between devices. Each of the three wires may be in one of three signaling states during transmission of a symbol over the C-PHY interface. Clock information is encoded in a sequence of symbols transmitted on the C-PHY interface and a receiver (RX) generates a clock signal from transitions between consecutive symbols. The maximum speed of the C-PHY interface and the ability of a clock and data recovery (CDR) circuit to recover clock information may be limited by the maximum time variation related to transitions of signals transmitted on the different wires of the communication link. A receiver may employ delay circuits to ensure that all of the conductors have assumed a stable signaling state before providing a sampling edge. The transmission rate of the link may be limited by the delay values used, and there is an ongoing need for clock generation circuits that can function reliably as signaling frequencies of multi-wire interfaces increase.
The performance of some known C-PHY clock and data recovery (CDR) designs in receivers (RXs) is limited by an internal closed loop timing relationship between input data and a delay feedback. For example, existing C-PHY CDR designs utilize phase detection and signal delay lines to intentionally skip one Unit Interval (UI) cycle and re-sample at the next cycle to synthesize a half UI rate operation to determine the recovered clock (RCLK). Such methods depend heavily on the accuracy of the delay line phase and frequency detection, which are subject to nonlinear effects and long signal latency. Such designs are also subject to numerous environmental and physical variations that affect performance such as process/temperature variations, channel length, or lane operation speed. Thus, it would beneficial to provide a CDR that does not depend on delay line phase and frequency detection to improve performance of the CDR.